DESIGN ENGINEER in IVRS INNOVATORS PVT LTD
Singapore, Singapore
Current:IVRS INNOVATORS PVT LTD
Education:BACHELOR OF ENGINEERING AND TECHNOLOGY
Job Experience
DESIGN ENGINEER
IVRS INNOVATORS PVT LTD
June 2010 to August 2013
Proficient in designing complex FPGA using Verilog HDL,logic & timing simulation,timing closure, hardware debugging , design verification and testing
Education
BACHELOR OF ENGINEERING AND TECHNOLOGY
ANNA UNIVERSITY (India)September 2006 to June 2013
Languages
English
Advanced
German
Basic
IT skills
Xilinx ISE , Quartex II (Altera)
Medium
Mat lab
Basic
Modelsim SE
Advanced
verilog
Advanced
c++
Medium
C language
Advanced
Ms Office
Advanced
Other Skills
More VAITHIYANATHASAMY
Career Goals
Industries of interest
Areas of interest
Availability to travel and work outside the city
No